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Forum Index : Microcontroller and PC projects : RS232 TTL SIGNAL GENERATOR
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OA47 Guru  Joined: 11/04/2012 Location: AustraliaPosts: 1043 |
I have a project that uses a Pi Pico to generate a TTL RS232 SIGNAL STREAM and has proven very handy over time. I wanted to incorporate a signal sniffer to identify the rate and bit length of a signal under test. I have used a sample and test procedure that will go through each data rate from 150 to 921600, 7 or 8 bits and 0-2 stop bits. The software tests for a string of ascii characters and when a match is found it reports that rate and bit length. The issue is that it takes an enormous time to accomplish if the sample is at the end of the sweep.  To improve efficiency and accuracy I have thought about measuring the average frequency of the bit stream and honing in on the bit formation of the stream. Rather than rely on AI, I thought BSI may be much more helpful so I was wondering if there could be some input in structuring a routine to accomplish the task. OA47 |
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rrroonn Newbie  Joined: 08/02/2026 Location: AustraliaPosts: 10 |
I think I would capture some pulses, the shortest pulse should give the baud rate away. If all else fails, remain flexible and maintain a sense of humour |
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phil99 Guru Joined: 11/02/2018 Location: AustraliaPosts: 3076 |
CSub LOG would have been perfect for that as it captures the timing of every transition in a bitstream in an array. However it (and most CSubs) is version specific so you would need to compile it for the firmware version you are using. Another option is the PULSIN() function. Load 2 dozen or so negative pulse times into an array then repeat with positive pulses. The baud rate can then be calculated from the shortest pulse. The longest high pulses (for TTL) may indicate the gaps between bytes. The number of shortest pulses that could fit between those gaps might be used to calculate the total number of bits. Bytes that are all 1 or all 0 may scupper that idea so would require testing. Another possibility is to use PIO. In the manual, Apendix F, EXAMPLE PROGRAM 3 is Volhout's 6 channel logic analyzer which could be adapted to capture 6 serial bitstreams at once. Edited 2026-03-16 13:58 by phil99 |
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| Volhout Guru Joined: 05/03/2018 Location: NetherlandsPosts: 5785 |
Hi Phil, Initially measuring pulse width is better than the proposed serial port logic analyzer(*). Baudrates vary from 50 to 3meg. That is 1:80000 ratio. The logic analyzer would need to switch samplerates, for it not to run out of memory. But yes, when you are in the correct range it can be used to do some automatic determining of baudrate, 7/8 bits, 1/2 stopbits, parity, etc... Volhout (*) but PicoLA is easier to "tune" and trigger. PicomiteVGA PETSCII ROBOTS |
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