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Forum Index : Microcontroller and PC projects : About time the ArmmiteH7 got some TLC: V5.07.01 betas

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disco4now

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Joined: 18/12/2014
Location: Australia
Posts: 971

Posted: 11:01pm 04 Mar 2023

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Hi Peter,
I am wondering if this will explain why loading V5.05 first will let it run.
The note in blue I discovered somewhere while getting the code to work on the 100 pin H7.
The line in red is included in the source for the CMM2 and H7 5.05 but not in the H7 5.07 source. I had to add it to get the clock going on the 100 pin version. (Also had to set drive to __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW); to make it work with the 100 pin board with a crystal.)

Gerry

void SystemClock_Config(void)
{

RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;

/**Supply configuration update enable
*/
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** Configure the main internal regulator output voltage
*/
if(HAL_GetREVID()==0x1003)__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
else __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);

while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/**Configure LSE Drive Capability
*/

/**
* @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
* @note As the LSE is in the Backup domain and write access is denied to
* this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
* (to be done once after reset).
* @note On STM32H7 Rev.B and above devices this can't be updated while LSE is ON.
* @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
* This parameter can be one of the following values:
* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
* @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
* @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
* @retval None
*/

HAL_PWR_EnableBkUpAccess(); //Need to enable access to change LSEDRIVE
//__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);
//__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
//__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW);
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);

/**Macro to configure the PLL clock source
*/

Latest F4 Latest H7 FotS

KeepIS

Guru

Joined: 13/10/2014
Location: Australia
Posts: 1828

Posted: 02:22am 05 Mar 2023

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Finally have a result: One unit has a fault where Vbat Pin draws 90ma from the backup battery when power is removed. Again correct link removed and confirmed. I will have to trace the board to see if there is a fault causing a path to MCU pwr.

To get V5.07.01b0 to run (communicate) I have to do the following, which works on both units every time.

BTW I did a number of full flash erases and it seems to make no difference to the sequence needed to get it running.

1: Drag Drop V5.05.11 into NOD_H743ZI2

2: Connect to console at 38400 and confirm it works - does every time.

3: Now drag drop V5.07.01b0 into NOD_H743ZI2

4: Connect to Console at 115200 - works every time.

In the end I only needed to press reset after each load when connecting a console coms program. Ctrl-C from Console is ignored sometimes, OK once connection is established. Only does this with the V2 boards?

NANO Inverter: Full download - Only Hex Ver 8.1Ks

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